1. Field of the Invention
The present invention relates to a system for parallel data transmission, and more particularly, to a system and a method for parallel data transmission in which the data transmission is controlled by a master device according to the status of a slave device.
2. Description of the Related Art
FIG. 1 is a block diagram of a conventional system for parallel data transmission. In FIG. 1, the system for parallel data transmission 10 includes a master device 11 and a slave device 13, wherein the master device 11 can be a microcontroller, and the slave device 13 can be an external memory device (e.g. a program memory, a data memory, or a peripheral device). An address signal add is transmitted through an address bus and a data signal da is transmitted in parallel through a data bus between the master device 11 and the slave device 13. In addition, unidirectional control signals such as a read signal rd. a write signal wr and an address latch enable signal ale are also transmitted between the master device 11 and the slave device 13. That is, the control signals are transmitted only from the master device 11 to the slave device 1 3.
FIG. 2 is a timing diagram indicating the signal transmission in the system for parallel data transmission 10 of FIG. 1. In FIG. 2, when the master device 11 intends to read the data from the slave device 13, the master device 11 first transmits an address latch enable signal ale at time point T1, and then transmits the address of the data to be read (i.e. the address signal add) to the address bus at time point T2. Then, the slave device 13 latches the address signal add after it has been received at time point T3. When the master device 11 transmits the read signal rd at time point T4, the slave device 13 transmits data corresponding to the latched address (i.e. the data signal da) to the data bus after the slave device 13 has received the read signal rd at time point T5. Finally, the master device 11 reads the data signal da at time point T6.
Similarly, when the master device 11 intends to write data to the slave device 13, the master device 11 first transmits the address latch enable signal ale at time point T1, and then transmits the address of the data to be written (i.e. the address signal add) to the address bus at time point T2. Then, the slave device 13 latches the address signal add after it has been received at time point T3. When the master device 11 transmits the write signal wr at time point T4, the master device 11 transmits the data to be written (i.e. the data signal da) to the data bus at time point T5. Finally, after the slave device 13 has received the write signal wr, the data signal da is written to positions corresponding to the latched address at time point T6.
When the slave device 13 malfunctions or does not exist, the conventional method mentioned above is not able to resolve the problem of erroneous read/write operation because the status of the slave device 13 is not known by the master device 11, and the whole system may fail to function properly in such a situation.